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Sequential Code Parallelization for Multi-core Embedded Systems: A Survey of Models, Algorithms and Tools

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dc.contributor.author Castro Godínez, Jorge Alberto
dc.date.accessioned 2015-08-20T23:58:17Z
dc.date.available 2015-08-20T23:58:17Z
dc.date.issued 2014
dc.identifier.citation Castro Godínez, J. A. (2014). Sequential Code Parallelization for Multi-core Embedded Systems: A Survey of Models, Algorithms and Tools. (Tesis, Master of Science in Electronics Engineering Major on Embedded Systems). Cartago: Electronics Engineering School, Instituto Tecnológico de Costa Rica. es_ES
dc.identifier.uri http://hdl.handle.net/123456789/47
dc.description Tesis, Master of Science in Electronics Engineering Major on Embedded Systems, Instituto Tecnológico de Costa Rica. es_ES
dc.description.abstract In recent years the industry experienced a shift in the design and manufacture of processors. Multiple-core processors in one single chip started replacing the common used single-core processors. This design trend reached the develop of System-on-Chip, widely used in embedded systems, and turned them into powerful Multiprocessor System-on-Chip. These multi-core systems have presented not only an improvement in performance but also in energy e ciency. Millions of lines of code have been developed over the years, most of them using sequential programming languages such as C. Possible performance gains of legacy sequential code executed in multi-core systems is limited by the amount of parallelism that can be extracted and exploit from that code. For this reason many tools have been developed to extract parallelism from sequential program and produce a parallel version of the original code. Nevertheless, most of these tools have been designed for high-performance computing systems rather than for embedded systems where multiple constraints must be considered, and a reduction in the execution time is not the only desirable objective. Due there is no de nitive solution for parallelizing code, especially for multi-core embedded systems, this work aims to present a survey on some di erent aspects involved in parallelizing code such as models of code representation, code analysis, parallelism extraction algorithms, parallel programming. Also existing parallelizing tools are presented and compared. This work ends with a recommended list of important key aspects that should be consider when designing and developing a parallelizing compiler, automatic or semiautomatic, for multi-core embedded systems; and when using existing tools to use them es_ES
dc.description.sponsorship I have to recognize and deeply thank to the MICITT (Ministerio de Ciencia, Tecnolog a y Telecomunicaciones), the CONICIT (Consejo Nacional para Investigaciones Cient cas y Tecnol ogicas) and the Fondo de Incentivos, that made possible the funding for my master studies, by means of a scholarship es_ES
dc.format DISPONIBLE EN FORMATO DIGITAL
dc.language.iso en es_ES
dc.relation.ispartofseries T00523
dc.subject ALGORITMOS es_ES
dc.subject SISTEMAS EMBEBIDOS es_ES
dc.subject LENGUAJES DE PROGRAMACION es_ES
dc.subject SISTEMAS MULTI-CORE INTEGRADOS es_ES
dc.subject INGENIERIA ELECTRONICA es_ES
dc.title Sequential Code Parallelization for Multi-core Embedded Systems: A Survey of Models, Algorithms and Tools es_ES
dc.type Thesis es_ES


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